“CMOS” refers to both a particular style of digital circuitry design, and the family of processes used to implement that circuitry on IC “chips” or “die”. CMOS logic uses a combination of p-type and n-type metal-oxide-semiconductor field-effect transistors (MOSFETs) to implement logic gates and other digital circuits found in computers, telecommunication equipment, and signal processing equipment. Typical commercial CMOS ICs include millions (or hundreds of millions) of n-type and p-type MOSFETS.
Most CMOS IC manufacturers (aka, “fabs”) generate standardized process “flows” for generating CMOS ICs on monocrystalline silicon wafers. Each CMOS process flow includes a series of processing steps (e.g., material deposition, photolithographic exposure, and etching) that are required to produce a desired CMOS IC product. Standard CMOS process flows are typically developed to produce “normal” CMOS IC devices (i.e., CMOS IC devices that comprise mainly volatile n-type and p-type MOSFETS) using a minimum number of processing steps in order to minimize overall production costs. Significant effort is typically expended by each manufacturer to make their standard CMOS process flow as time and cost efficient as possible. Once a standard CMOS flow is optimized, it can typically be used to make a large number of CMOS IC designs merely by providing a different set of photolithography masks for each IC design, and then repeating the standard CMOS process flow using the selected set of photolithography masks.
Although most standard CMOS process flows facilitate the inclusion of non-MOSFET circuit components into the CMOS IC products, a problem arises when a circuit design requires a component that cannot be produced by the standard CMOS process flow. In this case, the CMOS process flow must be modified at great expense to include additional steps in order to produce the needed circuit component. It is therefore desirable to develop methods for producing the non-standard circuit component using the steps of the existing CMOS process flow. When this goal is not possible, it is desirable to develop methods for non-standard circuit components that minimize the number of changes to the existing CMOS process flow.
Non-volatile memory (NVM) or “floating gate” cells represent one type of non-standard circuit component that is often needed in large scale CMOS ICs. In contrast to volatile (aka primary storage) memory such as SRAM based on typical n-type and p-type MOSFETs, which require continuous power to retain stored information, NVM cells are able to retain a stored state even when power to an IC is turned off, thereby allowing the IC to “remember” important operating conditions and information upon restart. Several types of NVM cells have been developed that can be produced with minimal changes to a standard CMOS process flow.
There is a currently a need for low cost, small size, many-times programmable (MTP) NVM cells that can be implemented using standard CMOS processes (or with minimal changes). That is, there are small, low-cost one-time-programmable (OTP) memories in the range of one to a few Mbits that can be fabricated with no additional masks to a standard CMOS process (e.g., antifuse memories produced by Kilopass Technology Inc. of Santa Clara, Calif., USA, and Sidense Corp. of Ottawa, Ontario, Canada). However, these OTP memories are not favored in the market because they cannot be re-programmed to implement code changes that are often needed to achieve minimal “time-to-market” for numerous designs employing NVM cells to control IC operations. Conversely, MTP and few-times-programmable (FTP) embedded NVM arrays are available, but existing FTP and MTP solutions are problematic for reasons detailed below, but in general because such MTP and FTP NVM cells require a large deviation from standard CMOS process flows, or have a cell size that is too large (i.e., providing FTP or MTP NVM arrays having a density ranging from 0.5 Mbit to 2 Mbit is proving to be a challenge to the semiconductor industry).
One type of MTP embedded NVM cell is the NROM memory cell based on charge trapping in ONO stack is disclosed in U.S. Pat. No. 5,768,192 (Saifun Semiconductor, Tower Semiconductor trademark: microFlash®). A problem with this approach is that these cells require a complex manufacturing process with N+ drain and source bit lines different from diffusions of n-channel MOS transistor. Special high voltage circuitry is also needed to provide voltages of the order of 8-9V for NROM programming and erase. These differences require 11-12 additional masks to the core CMOS process flow, thus making this technology expensive to implement.
Another type of MTP embedded NVM cell uses an H-array architecture that employs a CMOS-type transistor with an ONO dielectric (see, e.g., U.S. Pat. No. 6,765,259). This type of NVM cell architecture provides excellent area utilization, but requires special high voltage circuits to perform program and erase operations. That is, standard CMOS devices does not support the high program/erase voltages required by these cells, and therefore additional masks and processing steps are needed to provide suitable devices. This H-array architecture can also suffer from disturbs during programming and read of the multiple cells that share the same drain contact in the word-line direction. These disturbs can be inhibited, but this requires additional complicated circuit design to provide inhibition voltages to the neighbor cells in the array.
What is needed is an embedded MTP NVM cell that is small in size (i.e., high density), immune to disturbs, can be produced using a standard CMOS process flow having a single polysilicon layer with a minimal number of additional masks, and exhibits high endurance.